• GURRALA LAKSHMI APARNA
• A.B. CHANDRIKA

Quantum-dot cellular automata (QCA) are an attractive emerging technology suitable for the development of ultra-dense-low-power high-performance digital circuits. Efficient solutions have recently been proposed for several arithmetic circuits, such as adders, multipliers, and adders. Nevertheless, since the design of digital circuits in QCA still poses several challenges, novel implementation strategies and methodologies are highly desirable. This paper proposes a new design approach oriented to the implementation of binary adders in QCA. New formulations of basic logic equations required to perform the comparison function are proposed. The new strategy has been exploited in the design of two different adder architectures and for several operands word lengths. With respect to existing counterparts, the adders proposed here exhibit significantly higher speed and reduced overall area. The proposed scheme, we deal with 32-bit numbers with less number of resources unlike conventional adders, which leads to the realization of low power and area efficient adder. This adder can be widely used in central processing units (CPUs) and microcontrollers.

LOW DESIGN IMPLEMENTATION AREA RIPPLE CARRY ADDER IN QUANTUM DOT CELLULAR AUTOMATA

"LOW DESIGN IMPLEMENTATION AREA RIPPLE CARRY ADDER IN QUANTUM DOT CELLULAR AUTOMATA", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.6, Issue 6, page no.376-381, June 2019, Available :http://www.jetir.org/papers/JETIR1907C15.pdf

"LOW DESIGN IMPLEMENTATION AREA RIPPLE CARRY ADDER IN QUANTUM DOT CELLULAR AUTOMATA", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.6, Issue 6, page no. pp376-381, June 2019, Available at : http://www.jetir.org/papers/JETIR1907C15.pdf