• Raj Kumar Singh
• Braj Kishor
• Ambresh Patel

In CMOS, a flip-flop or latch is a circuit that has two stable states and can be used to store state information. The most fundamental sequential circuit type that we will ponder is known as the Flip-Flop. True single-phase clock (TSPC) method of reasoning has found wide use in advanced plan. This paper proposed 18-transistor single-phase clocked (TSPCFF) design at ultra low power with 50nm technology. Simulation is done using microwind software. Simulated result shows that proposed design gives reduced area, time and power than existing design.

TSPC, VLSI, Flip-Flop, Clock, RAM,ROM, SRAM, DRAM

"Design and Parameter Enhancement of Ultra-Low Power 18-Transistor Single-Phase Clocked Flip-Flop ", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.6, Issue 6, page no.827-832, June 2019, Available :http://www.jetir.org/papers/JETIR1907C77.pdf

"Design and Parameter Enhancement of Ultra-Low Power 18-Transistor Single-Phase Clocked Flip-Flop ", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.6, Issue 6, page no. pp827-832, June 2019, Available at : http://www.jetir.org/papers/JETIR1907C77.pdf