• Priya Sikarwar
• Pankaj Shrivastava

This paper compares the performance of low power 9T SRAM cell, which includes performance parameters such as the Average write delay and writes power product delay, read the behavior of each SRAM cells are examined. Low power 9T SRAM cell at 90nm technology always consumes lowest Average power; improve read stability as compared to the conventional 6T SRAM cell. The aim of this paper is to reduce the low power, improve the reading behavior of the different SRAM cell structures using cadence tool at 90nm technology. DG FINFET techniques have been employed to reduce the power consumed by the SRAM cell. The results show that the DG FINFET based SRAM cell is the best performer in terms of power consumption. We investigate the use of Double Gate FINFET technology provides low leakage and high-performance operation by utilizing high speed and low thresh hold voltage transistors for the logic cell

CMOS, 9T SRAM cell, Low Power, Average write delay, write power product delay, Cadence

"Design and Analysis of Low Power 9T SRAM cell using DG FINFET ", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.6, Issue 6, page no.397-400, June 2019, Available :http://www.jetir.org/papers/JETIR1907P58.pdf

"Design and Analysis of Low Power 9T SRAM cell using DG FINFET ", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.6, Issue 6, page no. pp397-400, June 2019, Available at : http://www.jetir.org/papers/JETIR1907P58.pdf