• SATYAM BHARDWAJ
• SWATI AGRAWAL
• RAHUL NEMA

Vedic mathematics is the name given to the ancient Indian system of mathematics that was rediscovered in the early twentieth century from ancient Indian sculptures (Vedas). This paper proposes the design of high speed Vedic Multiplier using the techniques of Vedic Mathematics that have been modified to improve performance. The ever increasing demand in enhancing the ability of processors to handle the complex and challenging processes has resulted in the integration of a number of processor cores into one chip. Still the load on the processor is not less in generic system. This load is reduced by supplementing the main processor with Co- Processors, which are designed to work upon specific type of functions like numeric computation, Signal Processing, Graphics etc. The speed of ALU depends greatly on the multiplier.Vedic Mathematics is the ancient system of mathematics which has a unique technique of calculations based on 16 Sutras. Employing these techniques in the computation algorithms of the coprocessor will reduce the complexity, execution time, area, power etc. This work presents different multiplier architectures. Multiplier based on Vedic Mathematics is one of the fast and low power multiplier.

Vedic mathematics ,Urdhva Tiryakbhyam Sutra ,Vedic multiplier

"IMPLEMENTATION OF A LOW AREA AND FAST SPEED MULTIPLIER FOR ALU USING VEDIC MATHEMATICS", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.6, Issue 6, page no.239-244, June 2019, Available :http://www.jetir.org/papers/JETIR1908036.pdf

"IMPLEMENTATION OF A LOW AREA AND FAST SPEED MULTIPLIER FOR ALU USING VEDIC MATHEMATICS", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.6, Issue 6, page no. pp239-244, June 2019, Available at : http://www.jetir.org/papers/JETIR1908036.pdf