• S.md. Abdul Azeez
• B.C. Vengamuni
• Dr.D.Vishnu Vardhan

The design-cycle of VLSI-chips consists of different consecutive steps from high-level synthesis (functional design) to production (packaging).This project aims to implement a physical design flow from netlist to gdsii that starts from floorplan, placement, CTS, routing and ends with physical verification. The main objective of this project is to fix the violations those results in the implementation of Volcano SoC such as crosstalk, slew violations, congestion and other signal integrity issues. Results show that the proposed steps eliminate these issues and clear the physical verification checks such as DRC, LVS static and IR and antenna design rule. Further the resultant optimized design meets the timing constraints and minimizes area to obtain a design suitable for manufacture. Here in this design we have used the inputs given by the synthesis team and further physical design flow has been carried out in a proper physical design flow i.e. from import design, floor plan further placement till signoff using the Physical design tools. At each stage checks are done such as timing , quality of report, congestion, routing etc.

Creating Bounds, Magnet Placement Timing Driven Placement, Congestion Driven Placement , CTS, Congestion, Path grouping

"Physical Design Implementation of Volcano SoC with timing closure using 28nm Technology", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.6, Issue 6, page no.831-839, June 2019, Available :http://www.jetir.org/papers/JETIR1908124.pdf

"Physical Design Implementation of Volcano SoC with timing closure using 28nm Technology", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.6, Issue 6, page no. pp831-839, June 2019, Available at : http://www.jetir.org/papers/JETIR1908124.pdf