• Rahul Patel
• Hema Singh

This paper review of Bit Linear Feedback Shift Register which generates pseudo-random test patterns as the input bit is a linear function of its previous state. The total number of random state generated on LFSR depends on the feedback polynomial. As it is simple counter so it can count maximum of 2n -1 by using maximum feedback polynomial. Here in this paper we study of 16-bit different types of shift register on FPGA by using VHDL and analysis the behaviour of randomness. The analysis is conceded out to find number of gates, memory and speed requirement in FPGA as the number of bits is increased. Also, the simulation problem for long bit LFSR on FPGA is presented. The design is simulated and synthesized in Xilinx software.

Serial in Serial Output (SISO), Serial in Parallel out, Parallel in Serial out, Parallel in Parallel Out

"Comparative Study of Different Types of Shift Register Based on Reversible Logic Gate ", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.6, Issue 6, page no.135-139, June 2019, Available :http://www.jetir.org/papers/JETIR1908172.pdf

"Comparative Study of Different Types of Shift Register Based on Reversible Logic Gate ", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.6, Issue 6, page no. pp135-139, June 2019, Available at : http://www.jetir.org/papers/JETIR1908172.pdf