• Kanchan Kumar
• Dr. Bharti Chourasia

Flip-Flops (FFs) are basic storage elements used extensively in digital system designs. In the existing flip flop design 19 and more transistors were used to design. It increases the power consumption delay and time performance. So its need to reduce the above mentioned problems. This paper review of ultralow power true single phase clocking flip flop designs achieved using fewer transistors. The transistor count is reduced by using logic structure reduction scheme.

"Review of Low Power Transistor Single Phase Clocked Flip-Flop", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.6, Issue 6, page no.68-72, June-2019, Available :http://www.jetir.org/papers/JETIR1908762.pdf

"Review of Low Power Transistor Single Phase Clocked Flip-Flop", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.6, Issue 6, page no. pp68-72, June-2019, Available at : http://www.jetir.org/papers/JETIR1908762.pdf