UGC Approved Journal no 63975

ISSN: 2349-5162 | ESTD Year : 2014
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Published in:

Volume 6 Issue 6
June-2019
eISSN: 2349-5162

UGC and ISSN approved 7.95 impact factor UGC Approved Journal no 63975

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Published Paper ID:
JETIR1908C96


Registration ID:
303135

Page Number

761-773

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Title

Power Efficient and Performance Comparisons of Diverse CMOS Structure of 2:1 MUX using DG FINFET Technique

Abstract

In this paper, we suggest 2:1 MUX architecture with low power high speed with the following logics: Static CMOS logic, Pseudo NMOS logic, CMOS Domino logic, and also Dual Rail Domino logic using DG FINFET (Double Gate Fin Shaped Field Effect Transistor) Technique. The portability was upgraded in gadgets with taller balances because of increment tensile stress. The urgent barriers to scaling of mass CMOS gate lengths comprise short channel impacts, ideal current, entryway dielectric spillage, and devices for the different devices. However, the DG FINFET outline provides improved power over short channel impacts, low spillages & improved yields. Results demonstrate that CMOS Domino Logic 2:1 MUX with the DG FINFET is the most efficient architecture in comparison with other family logic circuits since average power consumption is less than that of Power Delay Product (PDP) and other logic families. However, trade-offs b/w static CMOS logic & domino logic are concluded that can be ignored when taking into consideration total performance. Because DG FINFET Domino logic is above another logic family, this study shows that DG Domino logic allows any of higher MUX including low-power delay with PDP levels. The designed circuits are realized in a standard 90nm process technology and use 0.7V supply voltage. Our optimization circuitry using the proposed method reduces power consumption and leakage current by a significant amount of multiplexer circuit.

Key Words

MUX, Pseudo NMOS logic, Static CMOS logic, CMOS Dual-Rail Domino logic, and CMOS Domino logic Low Power, Cadence, Leakage Current, Delay

Cite This Article

"Power Efficient and Performance Comparisons of Diverse CMOS Structure of 2:1 MUX using DG FINFET Technique ", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.6, Issue 6, page no.761-773, June-2019, Available :http://www.jetir.org/papers/JETIR1908C96.pdf

ISSN


2349-5162 | Impact Factor 7.95 Calculate by Google Scholar

An International Scholarly Open Access Journal, Peer-Reviewed, Refereed Journal Impact Factor 7.95 Calculate by Google Scholar and Semantic Scholar | AI-Powered Research Tool, Multidisciplinary, Monthly, Multilanguage Journal Indexing in All Major Database & Metadata, Citation Generator

Cite This Article

"Power Efficient and Performance Comparisons of Diverse CMOS Structure of 2:1 MUX using DG FINFET Technique ", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.6, Issue 6, page no. pp761-773, June-2019, Available at : http://www.jetir.org/papers/JETIR1908C96.pdf

Publication Details

Published Paper ID: JETIR1908C96
Registration ID: 303135
Published In: Volume 6 | Issue 6 | Year June-2019
DOI (Digital Object Identifier):
Page No: 761-773
Country: Gwalior, Madhya Pradesh, India .
Area: Engineering
ISSN Number: 2349-5162


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