• Nasir Husain
• Dr. Bharti Chourasia

Multiplier is one in every of the foremost wide used arithmetic knowledge path operation in modern digital design. In the state of art Digital Signal process and graphics applications, multiplication is an important and computationally intensive operation. This paper proposed design and implementation of 64-Bit ROBA multiplier with low power, area and high speed. Existing 16 bit and 32 bit multipliers are using for signed numbers. Proposed multiplier support both signed and unsigned number as well as provide better performance than existing multipliers.

ROBA, VLSI, Multiplier, Speed, power.

"Design and Implementation of 64-Bit ROBA Multiplier with low Power and Area ", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.7, Issue 2, page no.187-191, February-2020, Available :http://www.jetir.org/papers/JETIR2002030.pdf

"Design and Implementation of 64-Bit ROBA Multiplier with low Power and Area ", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.7, Issue 2, page no. pp187-191, February-2020, Available at : http://www.jetir.org/papers/JETIR2002030.pdf