UGC Approved Journal no 63975(19)

ISSN: 2349-5162 | ESTD Year : 2014
Call for Paper
Volume 11 | Issue 4 | April 2024

JETIREXPLORE- Search Thousands of research papers



WhatsApp Contact
Click Here

Published in:

Volume 7 Issue 5
May-2020
eISSN: 2349-5162

UGC and ISSN approved 7.95 impact factor UGC Approved Journal no 63975

7.95 impact factor calculated by Google scholar

Unique Identifier

Published Paper ID:
JETIR2005418


Registration ID:
233424

Page Number

747-752

Share This Article


Jetir RMS

Title

Design of High Speed Synchronous Counter Using BICMOS Logic

Abstract

In most of the digital systems counter is a basic and essential component so it is important to design an efficient counter in terms of delay and power. In this paper BICMOS logic has been used for the implementation of 4-bit synchronous counter. BICMOS is the combination of CMOS and Bipolar transistors and the purpose of choosing this logic for designing is to combine the advantages of both Bipolar and CMOS transistor logic. Latch up problem can be completely eliminated by using BICMOS logic. Cadence Virtuoso schematic editor is used to implement the proposed circuit and Cadence Virtuoso analog design environment is used for the simulation process. The estimated power for the proposed counter circuit is 85.07 μw and delay is 18.27 ns.

Key Words

BICMOS, Master-Slave D flip flop, Latch up.

Cite This Article

"Design of High Speed Synchronous Counter Using BICMOS Logic", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.7, Issue 5, page no.747-752, May 2020, Available :http://www.jetir.org/papers/JETIR2005418.pdf

ISSN


2349-5162 | Impact Factor 7.95 Calculate by Google Scholar

An International Scholarly Open Access Journal, Peer-Reviewed, Refereed Journal Impact Factor 7.95 Calculate by Google Scholar and Semantic Scholar | AI-Powered Research Tool, Multidisciplinary, Monthly, Multilanguage Journal Indexing in All Major Database & Metadata, Citation Generator

Cite This Article

"Design of High Speed Synchronous Counter Using BICMOS Logic", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.7, Issue 5, page no. pp747-752, May 2020, Available at : http://www.jetir.org/papers/JETIR2005418.pdf

Publication Details

Published Paper ID: JETIR2005418
Registration ID: 233424
Published In: Volume 7 | Issue 5 | Year May-2020
DOI (Digital Object Identifier):
Page No: 747-752
Country: Jaipur, Rajasthan, India .
Area: Engineering
ISSN Number: 2349-5162
Publisher: IJ Publication


Preview This Article


Downlaod

Click here for Article Preview

Download PDF

Downloads

0003082

Print This Page

Current Call For Paper

Jetir RMS