UGC Approved Journal no 63975(19)

ISSN: 2349-5162 | ESTD Year : 2014
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Published in:

Volume 7 Issue 6
June-2020
eISSN: 2349-5162

UGC and ISSN approved 7.95 impact factor UGC Approved Journal no 63975

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Published Paper ID:
JETIR2006536


Registration ID:
234671

Page Number

1404-1409

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Title

Reduced Power and Delay using Fault Tolerant Technique in Self Healing Architecture

Abstract

Hardware systems have been proposing imitations to biological organisms in the way they offer healing and recovery abilities. Digital systems with inspired homogeneous architecture have improved capabilities to compensate for any faults. Self-healing is defined by the ability of a system to detect faults or failures and fix them. The problems in current self-healing approaches is area overhead and scalability for complex structures considering they are based on redundancy and spare blocks. This project proposes a different approach for self-healing based on embryonic structures without a need for spare cells. The area overhead is lower compared to other approaches relying on spare cells. The proposed approach relies on time multiplexing two functions in one cell within one clock cycle. The reliability of the proposed technique is studied and compared to conventional system with different failure rates. This approach is capable of healing the cells where each cell can cover another neighbour failed cell at most. The area overhead for the proposed approach is much lower compared to other approaches using spare cell. The proposed architecture uses fault tolerant self healing architecture with embryonic reconfigurable hardware which helps in reducing the drawbacks of existing systems. The designs are synthesized by using Xilinx ISE 14.5 Tools and are functionally verified by using ISIM Simulation tool. The proposed algorithm implements the designin proposed when compared to existing design and 65% and 3% respectively

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"Reduced Power and Delay using Fault Tolerant Technique in Self Healing Architecture ", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.7, Issue 6, page no.1404-1409, June 2020, Available :http://www.jetir.org/papers/JETIR2006536.pdf

ISSN


2349-5162 | Impact Factor 7.95 Calculate by Google Scholar

An International Scholarly Open Access Journal, Peer-Reviewed, Refereed Journal Impact Factor 7.95 Calculate by Google Scholar and Semantic Scholar | AI-Powered Research Tool, Multidisciplinary, Monthly, Multilanguage Journal Indexing in All Major Database & Metadata, Citation Generator

Cite This Article

"Reduced Power and Delay using Fault Tolerant Technique in Self Healing Architecture ", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.7, Issue 6, page no. pp1404-1409, June 2020, Available at : http://www.jetir.org/papers/JETIR2006536.pdf

Publication Details

Published Paper ID: JETIR2006536
Registration ID: 234671
Published In: Volume 7 | Issue 6 | Year June-2020
DOI (Digital Object Identifier):
Page No: 1404-1409
Country: CHITTOOR, ANDHRA PRADESH, India .
Area: Engineering
ISSN Number: 2349-5162
Publisher: IJ Publication


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