• Rashmi Shrivastava
• Ashish duvey

In any design of digital circuit, The one of the most common & Important building blocks is Flip Flops. Power, performance, area are the factors that affecting the design. Efficient design must be optimized by three parameters. In a time constrained design the focus is on the optimization of power and performance. PPA (Power Performance Area) factors can be optimized by many techniques. In this paper low power 18-Transistor true single-phase clocking FF design is proposed. Master-Slave configuration is used to design the FF. It is designed using dynamic CMOS and complementary pass transistors logic. The FF is designed to reduce dynamic power consumption by avoiding floating internal nodes. The microwind and DSCH software is used for the implementation of the Flip Flop with supply voltage VDD of 1V and clock frequency of 500MHz. The FF design is implement on 50nm technology. The results of the power dissipation and the delay is compared with 19-TSPC Results of the proposed design was found that it is more efficient than the other compared FF designs. In comparison with TSPC, the PDP improvement of the proposed design was 68% and 73% in overall and clock dynamic power, respectively, and 27% lower leakage.

"Low-Power 18-Transistor True Single-Phase Clocking Flip-Flop Design Based on Logic Structure Reduction Schemes", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.7, Issue 10, page no.2938-2948, October-2020, Available :http://www.jetir.org/papers/JETIR2010384.pdf

"Low-Power 18-Transistor True Single-Phase Clocking Flip-Flop Design Based on Logic Structure Reduction Schemes", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.7, Issue 10, page no. pp2938-2948, October-2020, Available at : http://www.jetir.org/papers/JETIR2010384.pdf