• Pragati Ekhare
• Prof. Tejaswini Chetty

The Channel coding is commonly incorporated to obtain sufficient reception quality in advance wireless mobile communications transceiver to counter channel degradation due to inter-symbol interference, multipath dispersion High speed and high throughput hardware for encoder and decoder could be useful in communication field. Due to the channel achieving property, the GOLAY code has become one of the most favorable error-correcting codes. This paper presents VLSI Implementation of Extended Golay Code for Error Correcting Parallel Decoder FPGA-DSP Applications, which outperform the existing architectures in terms of speed and throughput. The Simulation is done using the Xilinx ISE 14.7 platform with Isim test bench.

Golay, Error, FPGA, DSP, VLSI, Correcting, Code, Wireless, Transceiver

"VLSI Architecture of Extended Golay Code for Error Correcting Parallel Decoder FPGA Applications ", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.9, Issue 4, page no.e381-e386, April-2022, Available :http://www.jetir.org/papers/JETIR2204451.pdf

"VLSI Architecture of Extended Golay Code for Error Correcting Parallel Decoder FPGA Applications ", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.9, Issue 4, page no. ppe381-e386, April-2022, Available at : http://www.jetir.org/papers/JETIR2204451.pdf