UGC Approved Journal no 63975(19)

ISSN: 2349-5162 | ESTD Year : 2014
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Published in:

Volume 9 Issue 5
May-2022
eISSN: 2349-5162

UGC and ISSN approved 7.95 impact factor UGC Approved Journal no 63975

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Published Paper ID:
JETIR2205A08


Registration ID:
403138

Page Number

j50-j56

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Title

A Clock Gating Technique Using Different Techniques

Abstract

In the design of ICs, power dissipation is an important parameter that indicates the need of Low Power circuits in modern VLSI design. In IC chip design various techniques invented for low power design. In several techniques Clock gating is one of widely used technique, which provides very effective solutions for reduction of dynamic power dissipation. Many researchers are modified clock gating techniques in many different ways. This paper included comparative analysis of power in Clock Divider circuit using different clock gating techniques. The look ahead clock gating based on auto gated flip flops method combines the previously three methods. Several techniques to reduce the power have been developed of which clock gating is predominant. This look ahead clock gating computes the clock enabling signals of each flip flop one cycle ahead of time, based on the present cycle data of those flip flops on which it depends. It avoids the tight timing constraints of auto gated and data driven by allotting a full clock cycle for the computation of the enabling signals and their propogation. A look ahead clock gating model is presented which is based on the auto gated flip flop. The comparison between the look ahead, data driven clock gating is done. This clock gating is very useful for reducing the power consumed by digital systems. Power consumption plays an important role in any integrated circuit and is listed as one of the top three challenges in international technology roadmap for semiconductor.

Key Words

Clock Gating, Flip-flop, Latch, Look ahead, Gate etc.

Cite This Article

"A Clock Gating Technique Using Different Techniques", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.9, Issue 5, page no.j50-j56, May-2022, Available :http://www.jetir.org/papers/JETIR2205A08.pdf

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2349-5162 | Impact Factor 7.95 Calculate by Google Scholar

An International Scholarly Open Access Journal, Peer-Reviewed, Refereed Journal Impact Factor 7.95 Calculate by Google Scholar and Semantic Scholar | AI-Powered Research Tool, Multidisciplinary, Monthly, Multilanguage Journal Indexing in All Major Database & Metadata, Citation Generator

Cite This Article

"A Clock Gating Technique Using Different Techniques", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.9, Issue 5, page no. ppj50-j56, May-2022, Available at : http://www.jetir.org/papers/JETIR2205A08.pdf

Publication Details

Published Paper ID: JETIR2205A08
Registration ID: 403138
Published In: Volume 9 | Issue 5 | Year May-2022
DOI (Digital Object Identifier):
Page No: j50-j56
Country: chittoor, Andhra Pradesh, India .
Area: Engineering
ISSN Number: 2349-5162
Publisher: IJ Publication


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