• Ashish Aman
• Abhishek Shrivastava

Flip-flops are frequently employed in low power VLSI systems to receive and maintain data in specific sequences throughout recurring clock intervals for a brief amount of time necessary for other circuits in a system. In this paper leakage current and leakage power of conventional D-type CMOS flip-flop at 90nm technology has been estimated and circuit systems to decrease Leakage in deep sub-micron such as Sizing of the transistor and Power Gating have been discussed and applied to conventional D-type CMOS flip-flop. By the sizing of the transistors in the D-type CMOS flip-flop, an optimized D-type CMOS flip-flop is obtained and evaluated, and established to be more efficient than the conventional D-type CMOS flip-flop. Then, Power Gating is used on the improved D-type CMOS flip-flop, and it is discovered to be the fastest and most efficient in terms of leakage power and leakage current. The verification results demonstrate that our enhancement, as compared to Power Gating flip-flops, significantly lowers energy consumption at low data switching activity while maintaining tolerable space and setup time costs. Using the Cadence tool at 90nm technology, the proposed design, and the existing design are both simulated.

Leakage Current, D-Flip Flop, Leakage Power, Power Gate Cadence, Delay, CMOS

"Performance and Analysis of Low Power D-type Flip Flop using Power Gating Techniques", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.9, Issue 8, page no.c327-c331, August-2022, Available :http://www.jetir.org/papers/JETIR2208235.pdf

"Performance and Analysis of Low Power D-type Flip Flop using Power Gating Techniques", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.9, Issue 8, page no. ppc327-c331, August-2022, Available at : http://www.jetir.org/papers/JETIR2208235.pdf