• Emani Pravallika
• Kesari Padma Priya

This paper proposes the Imprecise multiplier using Dual stage Compressor with reversable logic. The proposed dual stage compressor has universal gates which helps in reducing the area and power. An 8×8 multiplier is implemented in this paper. This multiplier is designed using Dual stage 4:2 Compressors in the Partial product accumulation stage and Parallel Prefix Adder in the final partial product addition stage. Using reversable logic gates helps in increasing the performance of the multiplier. The Dual stage 4:2 compressors have universal gates which decrease the area and power. Parallel prefix Adder decreases the delay in the final partial product addition. The proposed multiplier is measured in terms of area, delay and power. The effectiveness of the proposed method is synthesized and simulated using Xilinx Vivado 2018.3.

Wallace multiplier, Dual stage compressor, Parallel prefix adder, Reversable logic.

"Design of Imprecise multiplier using Dual stage compressor with Reversable logic", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.9, Issue 10, page no.d250-d257, October-2022, Available :http://www.jetir.org/papers/JETIR2210345.pdf

"Design of Imprecise multiplier using Dual stage compressor with Reversable logic", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.9, Issue 10, page no. ppd250-d257, October-2022, Available at : http://www.jetir.org/papers/JETIR2210345.pdf