• CH.SRAVANI
• CH.BHAVANA
• K.SOWMYA
• K.VAMSI
• P.MOUNIKA

In this project, a novel low power 16x16 bit multiplier based on the approximate Radix 256 booth encoder has been proposed. The proposed approximate radix-256 Booth encoding with partial encoding approach uses appropriately selected partial product pairs to resolve hard multiple issue and obtain a small error distance. The multiplier design based on the proposed Booth encoding exhibits better performance- accuracy tradeoff. A partial encoding approach is used to produce partial product pairs, which can be obtained easily by simple shifting and complementing operations. The exact encoding values are thus replaced by the sum of each corresponding partial product pair. The evaluation on DSP applications further validates its applicability for error-tolerant computing. The performance of the proposed work is evaluated in terms of power, delay and Power delay Product. The parametric analysis of the proposed work is also carried out to assess the impact of various parameters. The total work has been carried out using different CMOS technology 45nm using Xilinx Vivado tools.

Approximate computing, radix-256, Booth encoding, energy efficient.

" DESIGN OF APPROXIMATE RADIX 256 BOOTH ENCODING FOR DIGITAL SIGNAL PROCESSING", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.10, Issue 4, page no.m56-m60, April-2023, Available :http://www.jetir.org/papers/JETIR2304C07.pdf

" DESIGN OF APPROXIMATE RADIX 256 BOOTH ENCODING FOR DIGITAL SIGNAL PROCESSING", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.10, Issue 4, page no. ppm56-m60, April-2023, Available at : http://www.jetir.org/papers/JETIR2304C07.pdf