UGC Approved Journal no 63975(19)

ISSN: 2349-5162 | ESTD Year : 2014
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Published in:

Volume 10 Issue 4
April-2023
eISSN: 2349-5162

UGC and ISSN approved 7.95 impact factor UGC Approved Journal no 63975

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Published Paper ID:
JETIR2304C88


Registration ID:
514204

Page Number

m654-m659

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Title

Design and Performance Analysis of Low Power CECRL and CPFAL Diverse Full Adder Circuits

Abstract

Designing low-power, energy-efficient circuits using DG FINFET technology presents a formidable obstacle. This study describes internal logic structure and circuit operation for creating different Full adder cells utilizing DG FINFET and CMOS devices. A CMOS & DG FINFET-based diversified full adder (DFA) is constructed at transistor level. The cadence tool is used to do simulations in 90nm technology, and results are contrasted with those from a performance analysis of these DFA in 90nm DGFINFET technology. In comparison to DFA, DFA using DG FINFET methods achieves low leakage and current power for enhanced mobility & transistor scaling. This work evaluates and contrasts the power dissipation of standard CPFAL-based, CMOS, and CECRL-based CMOS circuits. The results are applied to redesign a circuit in which input power is assumed to come from a sinusoidal source of 0.7 V. In comparison with the conventional diverse full adder (DFA) circuit, the designed CECRL and CPFAL diverse full adder (DFA) circuit has lesser power dissipation and also for full adder conventional CMOS circuit with CECRL and PFAL based full adder respectively.

Key Words

CMOS, Diverse Full Adder, DG FINFET, Leakage Power, Area, Cadence

Cite This Article

"Design and Performance Analysis of Low Power CECRL and CPFAL Diverse Full Adder Circuits", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.10, Issue 4, page no.m654-m659, April-2023, Available :http://www.jetir.org/papers/JETIR2304C88.pdf

ISSN


2349-5162 | Impact Factor 7.95 Calculate by Google Scholar

An International Scholarly Open Access Journal, Peer-Reviewed, Refereed Journal Impact Factor 7.95 Calculate by Google Scholar and Semantic Scholar | AI-Powered Research Tool, Multidisciplinary, Monthly, Multilanguage Journal Indexing in All Major Database & Metadata, Citation Generator

Cite This Article

"Design and Performance Analysis of Low Power CECRL and CPFAL Diverse Full Adder Circuits", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.10, Issue 4, page no. ppm654-m659, April-2023, Available at : http://www.jetir.org/papers/JETIR2304C88.pdf

Publication Details

Published Paper ID: JETIR2304C88
Registration ID: 514204
Published In: Volume 10 | Issue 4 | Year April-2023
DOI (Digital Object Identifier):
Page No: m654-m659
Country: Gwalior, Madhya Pradesh, India .
Area: Engineering
ISSN Number: 2349-5162
Publisher: IJ Publication


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