• T.hemasundari
• D. Naresh Kumar

Arithmetic operations are significant in many applications, such as image processing. These operations are the most widely used multipliers, such as the Wallace tree and Karatsuba multipliers. But in all these multipliers, we have many problems, which are area consumption, delay etc., with an increase in the size of the multiplier. Hence, this paper proposed a modified Karatsuba multiplier using the rounding method. The simulation results reveal that the Proposed Multiplier (PM) provides better performance in terms of area and delay compared to existing designs. The proposed and existing designs are coded Verilog HDL and synthesized and simulated using Xilinx Vivado 2016.4 environment.

Karatsuba multiplier, Wallace Tree multiplier, rounding, adders, Shifters, Approximate computing.

"Efficient Design of Rounding-based Approximate Modified Karatsuba Multiplier", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.10, Issue 7, page no.b277-b281, July-2023, Available :http://www.jetir.org/papers/JETIR2307136.pdf

"Efficient Design of Rounding-based Approximate Modified Karatsuba Multiplier", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.10, Issue 7, page no. ppb277-b281, July-2023, Available at : http://www.jetir.org/papers/JETIR2307136.pdf