UGC Approved Journal no 63975(19)

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Published in:

Volume 10 Issue 8
August-2023
eISSN: 2349-5162

UGC and ISSN approved 7.95 impact factor UGC Approved Journal no 63975

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Published Paper ID:
JETIR2308411


Registration ID:
522295

Page Number

e87-e92

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Title

Design and Analysis of Low Power 7T SRAM 8x8 SRAM Memory Array with Quit Bit Line Technique

Abstract

This paper presents the lowest power 8X8 SRAM array that is designed to store 128 bits. Absolute arrays are equipped with ancillary devices including SRAM cells, write driver circuits, revived circuits, address decoders, and sense amplifiers. This documentation is for an 8X8 SRAM array that utilizes 7T SRAM cells and is ranked according to total power consumption. Location and obstructions have a significant role in determining SRAM's overall efficacy. The suggested architecture for an 8x8 SRAM array is similar to existing 8x8 SRAM arrays that use conservative 6T SRAM cells, with the addition of a single NMOS transistor placed between two cross-coupled inverters. These designs reduce static power in support mode. The cadence simulation device is exercised at 90nm technology for manipulation. The proportional research is completed in a sequence of Read, Write Access time, Leakage power consumption, and absolute Leakage power consumption. Utilizing the Quiet Bitline approach, in which the voltage of bit lines remains as low as possible to attain high speed with low power while operating at a temperature of 270C, we have optimized leakage current and low power of an SRAM memory array. With the use of a low-power, quiet-bit line method, all bit lines are kept at low voltages at all times. This prevents wasteful full-swing charging on the bit line one-side driving scheme, which is utilized for write operations, and for read operations, that employ precharged, free-pulling techniques

Key Words

SRAM, 7T SRAM Cell, Cadence, CMOS, Leakage Power.

Cite This Article

"Design and Analysis of Low Power 7T SRAM 8x8 SRAM Memory Array with Quit Bit Line Technique ", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.10, Issue 8, page no.e87-e92, August-2023, Available :http://www.jetir.org/papers/JETIR2308411.pdf

ISSN


2349-5162 | Impact Factor 7.95 Calculate by Google Scholar

An International Scholarly Open Access Journal, Peer-Reviewed, Refereed Journal Impact Factor 7.95 Calculate by Google Scholar and Semantic Scholar | AI-Powered Research Tool, Multidisciplinary, Monthly, Multilanguage Journal Indexing in All Major Database & Metadata, Citation Generator

Cite This Article

"Design and Analysis of Low Power 7T SRAM 8x8 SRAM Memory Array with Quit Bit Line Technique ", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.10, Issue 8, page no. ppe87-e92, August-2023, Available at : http://www.jetir.org/papers/JETIR2308411.pdf

Publication Details

Published Paper ID: JETIR2308411
Registration ID: 522295
Published In: Volume 10 | Issue 8 | Year August-2023
DOI (Digital Object Identifier):
Page No: e87-e92
Country: Gwalior, Madhya Pradesh, India .
Area: Engineering
ISSN Number: 2349-5162
Publisher: IJ Publication


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