UGC Approved Journal no 63975(19)

ISSN: 2349-5162 | ESTD Year : 2014
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Published in:

Volume 10 Issue 8
August-2023
eISSN: 2349-5162

UGC and ISSN approved 7.95 impact factor UGC Approved Journal no 63975

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Published Paper ID:
JETIR2308479


Registration ID:
523683

Page Number

e689-e693

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Title

Area Delay Analysis of CMOS Reversible Gate based Add-Sub Circuit for VLSI Application

Abstract

Full Adder is the heart of any central processing unit that is a core component employed in all the processors. The approach to minimize power loss from digital devices made researchers to focus on reversible logic. This paper presents area delay analysis of CMOS reversible gate based add-sub circuit for VLSI application. This design is compared with existing designs on some selected performance parameters such as total number of reversible gates, garbage outputs and quantum cost. The proposed design for 8-bit adder-subtractor circuit using reversible approach simulated using Modelsim tool and synthesised for Xilinx ISE 14.7.

Key Words

Adder, Xilinx, Reversible Realization, Delay, components, Gates

Cite This Article

"Area Delay Analysis of CMOS Reversible Gate based Add-Sub Circuit for VLSI Application", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.10, Issue 8, page no.e689-e693, August-2023, Available :http://www.jetir.org/papers/JETIR2308479.pdf

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2349-5162 | Impact Factor 7.95 Calculate by Google Scholar

An International Scholarly Open Access Journal, Peer-Reviewed, Refereed Journal Impact Factor 7.95 Calculate by Google Scholar and Semantic Scholar | AI-Powered Research Tool, Multidisciplinary, Monthly, Multilanguage Journal Indexing in All Major Database & Metadata, Citation Generator

Cite This Article

"Area Delay Analysis of CMOS Reversible Gate based Add-Sub Circuit for VLSI Application", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.10, Issue 8, page no. ppe689-e693, August-2023, Available at : http://www.jetir.org/papers/JETIR2308479.pdf

Publication Details

Published Paper ID: JETIR2308479
Registration ID: 523683
Published In: Volume 10 | Issue 8 | Year August-2023
DOI (Digital Object Identifier):
Page No: e689-e693
Country: Bhopal, MP, India .
Area: Engineering
ISSN Number: 2349-5162
Publisher: IJ Publication


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