• Rohit Kumar Dubey
• Prof. Braj Bihari Soni
• Prof. Rajeev Thakur

This paper presents a performance analysis of area and delay characteristics in CMOS reversible gate-based add–subtract circuits for VLSI applications. Reversible logic is explored as an energy-efficient alternative to conventional irreversible designs by minimizing information loss and reducing power dissipation. The proposed add–subtract architecture is implemented using CMOS reversible gates and evaluated in terms of silicon area utilization and propagation delay. Simulation results demonstrate that the reversible gate-based design achieves improved area efficiency and reduced delay compared to traditional CMOS add–subtract circuits, making it suitable for low-power and high-speed VLSI systems.

Reversible logic, CMOS, Add–Subtract, Area, Delay, VLSI

"Performance Analysis of Area and Delay in CMOS Reversible Gate-Based Add–Subtract Circuits for VLSI", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.10, Issue 8, page no.e689-e693, August-2023, Available :http://www.jetir.org/papers/JETIR2308479.pdf

"Performance Analysis of Area and Delay in CMOS Reversible Gate-Based Add–Subtract Circuits for VLSI", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.10, Issue 8, page no. ppe689-e693, August-2023, Available at : http://www.jetir.org/papers/JETIR2308479.pdf