UGC Approved Journal no 63975(19)

ISSN: 2349-5162 | ESTD Year : 2014
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Published in:

Volume 10 Issue 11
November-2023
eISSN: 2349-5162

UGC and ISSN approved 7.95 impact factor UGC Approved Journal no 63975

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Published Paper ID:
JETIR2311435


Registration ID:
528484

Page Number

e247-e252

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Title

Implementation of Power Efficient CMOS D Flip Flop using Leakage Reduction Technique

Abstract

Leakage power is of paramount importance in CMOS technology. Power consumption may be reduced and the battery backup time extended by reducing the voltage supplied to the designated circuit when it is in standby mode.CMOS D flip-flops (FFs) have a rather high-power consumption, and digital systems may benefit considerably by optimizing their FFs' power usage. A power-efficient CMOS D FF (PECDTG) using Transmission gate is proposed. The suggested PECD FF only performs precharges when they are necessary thanks to their input-aware precharge approach. Energy efficiency is maintained without increasing the PECDTG FF's size by floating node analyses and transistor level optimisation. D type CMOS flip flop circuits use an adapted SVL approach to suppress signals and lower power consumption from leakage currents while the device is in standby mode. Further, the suggested layout requires fewer clocked transistors, cutting down on both dynamic power usage and leakage current. The proposed FF uses less power than a regular CMOS D-type flip-flop at 10% data activity and 0.7 V supply voltage thanks to the use of 90- nm CMOS technology.

Key Words

CMOS, Leakage Power, D-Flip Flop (D-FF), Delay, Cadence, Current Leakage

Cite This Article

"Implementation of Power Efficient CMOS D Flip Flop using Leakage Reduction Technique ", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.10, Issue 11, page no.e247-e252, November-2023, Available :http://www.jetir.org/papers/JETIR2311435.pdf

ISSN


2349-5162 | Impact Factor 7.95 Calculate by Google Scholar

An International Scholarly Open Access Journal, Peer-Reviewed, Refereed Journal Impact Factor 7.95 Calculate by Google Scholar and Semantic Scholar | AI-Powered Research Tool, Multidisciplinary, Monthly, Multilanguage Journal Indexing in All Major Database & Metadata, Citation Generator

Cite This Article

"Implementation of Power Efficient CMOS D Flip Flop using Leakage Reduction Technique ", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.10, Issue 11, page no. ppe247-e252, November-2023, Available at : http://www.jetir.org/papers/JETIR2311435.pdf

Publication Details

Published Paper ID: JETIR2311435
Registration ID: 528484
Published In: Volume 10 | Issue 11 | Year November-2023
DOI (Digital Object Identifier):
Page No: e247-e252
Country: Gwalior, Madhya Pradesh, India .
Area: Engineering
ISSN Number: 2349-5162
Publisher: IJ Publication


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