• Monika Salis

This research work presents a novel optimization Technique to VLSI (Very Large-Scale Integration) floorplanning combining the Firefly and Tabu Search Techniques (FTS). This algorithm combines the exploration capabilities of the Firefly Algorithm with the local search capabilities of Tabu Search. The primary focus is on enhancing the floor planning process through the integration of the firefly algorithm. The proposed methodology aims to address the challenges associated with traditional floor planning techniques presented in the literature. By leveraging the firefly algorithm's optimization capabilities, the study demonstrates improvements in floor plan quality and efficiency. The results show that this approach has potential to contribute to more streamlined and effective VLSI design processes. The effectiveness of proposed optimization Technique is demonstrated with MATLAB R2021b software.

VLSI floorplanning, optimization, firefly algorithm, integrated circuits, optimization efficiency

"A Novel Optimization Technique for VLSI Floorplanning Using Firefly and Tabu Search", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.11, Issue 1, page no.e503-e511, January-2024, Available :http://www.jetir.org/papers/JETIR2401460.pdf

"A Novel Optimization Technique for VLSI Floorplanning Using Firefly and Tabu Search", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.11, Issue 1, page no. ppe503-e511, January-2024, Available at : http://www.jetir.org/papers/JETIR2401460.pdf