Abstract
Available Transfer Capability (ATC) between two points of a power system determines the maximum incremental power transfer that is possible while considering circuit limitations. It is estimated via a combination of existing commitments of transmission (ETC), total transfer capability (TTC) and transmission reliability margin (TRM), which are controlled via generator participation factors. Thus, efficient control of these participation factors can assist in improving ATC between different points of electrical circuits. Researchers have proposed multiple optimization models to perform this task, but most of these models use static rules, thus cannot be deployed for dynamically changing load requirements. To overcome this limitation, a novel Genetic Model for Maximization of ATC via optimum selection of participation factors is proposed in this text. The model uses line data, source bus, destination bus, and minimum participation needed for different sources in order to train a dynamic Genetic Model (GM), which assists in estimation of participation factors. These factors are optimized via continuous evaluation of Power Transfer Distribution Factor (PTDF), which is estimated by stochastic differential power factor calculations. Based on these stochastic calculations, different participation factors (PFs) for obtaining Maximum ATC levels are estimated, and each of these PFs are further evaluated for quality maximization under different bus configurations. The model also proposes a novel Learning Rate (LR) optimization method, which assists in selection of circuit-specific GM parameters. Due to use of the LR optimization method, transmission system designers can directly reconfigure underlying GM model by providing circuit parameters. This further reduces delay needed to identify optimum PF values for different circuit types. The model was tested & deployed under different standard bus configurations, and its efficiency was evaluated in terms of ATC improvement, Total Harmonic Distortion (THD), Power Efficiency, and computational delay performance. Based on this evaluation, the model was compared with various state-of-the-art models, and it was observed that the proposed model showcased 8.5% better ATC, 3.8% lower THD, 8.3% better power efficiency, and 19.2% lower delay under different configurations. This performance was observed to be consistent across different bus systems, thereby suggesting that the proposed model has high scalability, and can be used for a wide variety of deployments.