• Ravishankar Singh
• Amit Gupta
• Madan Gopal
• Rishikesh Tiwari

Abstract— Multiplication is a fundamental operation in digital signal processing, cryptography, and various computational tasks. The efficiency of multiplication directly impacts the overall performance of these applications. Traditional multiplication techniques such as array and Wallace tree multipliers often face challenges in terms of area overhead and speed. In recent years, iterative-based sequential multipliers have emerged as a promising alternative, offering improved performance and reduced resource utilization. This paper presents a comprehensive overview of iterative-based sequential multipliers, focusing on their design principles, architecture, and performance characteristics. Unlike conventional multipliers, which require complex hardware structures, iterative-based sequential multipliers employ a sequential approach, breaking down the multiplication process into simpler stages. This enables efficient resource utilization and facilitates high-speed operation. The proposed multiplier architecture comprises interconnected stages, each performing a specific computation step. By iteratively processing partial products, the multiplier achieves the desired multiplication result. Moreover, the sequential nature of the design enables pipelining, further enhancing throughput and reducing latency. Various optimization techniques, such as operand recoding and partial product reduction, are employed to minimize critical path delay and improve overall performance. Experimental results demonstrate the effectiveness of the iterative-based sequential multiplier in terms of speed, area efficiency, and power consumption. Comparative analysis with conventional multipliers showcases significant improvements in performance metrics, making it an attractive choice for applications demanding high-speed arithmetic operations within constrained hardware resources.In conclusion, iterative-based sequential multipliers offer a compelling solution for enhancing the efficiency and performance of multiplication operations in digital systems. Their simplicity, scalability, and adaptability make them suitable for a wide range of applications, from embedded systems to high-performance computing platforms. Further research in optimization techniques and architectural enhancements holds the potential to unlock even greater advancements in iterative-based sequential multiplication.

"Design and implementation of a fast sequential multiplier based on iterative addition architecture", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.11, Issue 4, page no.n264-n271, April-2024, Available :http://www.jetir.org/papers/JETIR2404D31.pdf

"Design and implementation of a fast sequential multiplier based on iterative addition architecture", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.11, Issue 4, page no. ppn264-n271, April-2024, Available at : http://www.jetir.org/papers/JETIR2404D31.pdf