• Subash.T
• Dr. P .ELAVARASAN
• SASIDHARAN B
• NAVEEEN M

A low-power CMOS dynamic OP-AMP is proposed for high frequency applications. Analog – digital converters (ADCs) are the converter electronic circuits which converts continuous signals into digital signals (binary data) for analyzing, estimation and transmission of signals. Device like transceiver uses an ADC in receiver part for converting a signal to digital form. However, high frequency applications like millimeter wave applications ADC consumes more power due to high frequency range. Therefore, a new adaptive power control dynamic (clocked regenerative) OP-AMP architecture is proposed with low power and high-speed performance for analog to digital converters. A low-power CMOS OP-AMP has been designed with optimized speed with total power of 30.25µW with supply voltage of 1V for ADC. The circuit is designed and simulated with 0.90µm CMOS technology.

"POWER REDUCTION OF DIGITAL-BASED ANALOG AMPLIFIERS USING CMOS TECHNIQUES", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.11, Issue 4, page no.o318-o324, April-2024, Available :http://www.jetir.org/papers/JETIR2404F47.pdf

"POWER REDUCTION OF DIGITAL-BASED ANALOG AMPLIFIERS USING CMOS TECHNIQUES", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.11, Issue 4, page no. ppo318-o324, April-2024, Available at : http://www.jetir.org/papers/JETIR2404F47.pdf