• Atharva Bagul
• Diksha Mahajan
• Smita Gohil
• Tarun Suryawanshi
• Pushpalata Aher

This research explores the potential of open source RISC-V processor cores for designing low-power IoT devices. RISC-V is an open source instruction set architecture (ISA), which offers flexibility and customization for IoT applications. This research investigates the performance of RISC-V in power saving techniques compared to traditional architectures. It presents case studies and analyses to demonstrate the RISC-V's effectiveness in various IoT scenarios, such as smart homes and wearable health monitoring. The results highlight the benefits and challenges of implementing RISC-V on IoT devices, and highlight its potential to optimise energy consumption and promote innovation in the IoT industry. Open-source RISC-V cores offer power efficiency and customization for IoT devices. They have advantages over traditional architectures such as low energy consumption, small size, high performance, and flexible security. The results of the research show that the RISC-V core can be customised to specific applications, increasing power efficiency. However, the legal, licensing and technical challenges of widespread adoption remain. Progress in reliable and safe execution, system-level use case support, and flexible hardware architectures can have a major impact on the future of IoT devices.

RISC, Power saving techniques, Low-power IoT devices, Open source processors.

"Exploring The Potential Of Open-Source RISC-V Cores For Low-Power IOT Devices.", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.11, Issue 5, page no.g129-g144, May-2024, Available :http://www.jetir.org/papers/JETIR2405618.pdf

"Exploring The Potential Of Open-Source RISC-V Cores For Low-Power IOT Devices.", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.11, Issue 5, page no. ppg129-g144, May-2024, Available at : http://www.jetir.org/papers/JETIR2405618.pdf