• Bogala Himasri
• Dr.P.Ramana Reddy
• Dr.G.Mamatha

The Serial Peripheral Interface (SPI) is a synchronous communication protocol known for enabling fast, full-duplex data exchange between microcontrollers and peripheral devices. Its high-speed performance makes it ideal for applications that require efficient and rapid data transfer. This paper presents the design and verification of an SPI controller integrated with the A2O Core, a fabless System-on-Chip (SoC) developed within the OpenPOWER processor architecture. The goal is to enhance the A2O Core’s capability to interface effectively with external peripherals. The controller is designed using Verilog HDL and verified through simulation and synthesis using the Xilinx Vivado toolset. The integration process involves creating a hardware description, functional verification, developing an AXI-compliant wrapper, and connecting the controller via an AXI interconnect to the A2O Core. This structured design approach enables scalable, high-speed peripheral communication and provides a reusable SPI interface suitable for future OpenPOWER-based processor implementations

A2O, SPI, AXI Interconnect, SoC, Verilog

"Design And Validation Of SPI Controller Integration For Open Power Processor Core Based Fabless System On Chip(Soc)", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.12, Issue 5, page no.i714-i717, May-2025, Available :http://www.jetir.org/papers/JETIR2505980.pdf

"Design And Validation Of SPI Controller Integration For Open Power Processor Core Based Fabless System On Chip(Soc)", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.12, Issue 5, page no. ppi714-i717, May-2025, Available at : http://www.jetir.org/papers/JETIR2505980.pdf