• Bahul Dev M
• Sujatha K

Analog-to-digital converters (ADCs) are a critical interface in modern sensor-centric electronic systems, playing an essential role in accurately digitizing analog signals for high-speed data processing. Ground Penetrating Radar (GPR) applications demand ADCs with high resolution, moderate to high sampling rates, and robust resilience to noise and environmental variations. This project presents the design and top-down behavioral modeling of a 12-bit, 40 MSPS Successive Approximation Register (SAR) ADC targeting GPR systems using SCL 180nm CMOS technology. The methodology adopts a modular design flow, beginning with architecture selection and the comparative study of various SAR sub-circuits—capacitive DACs, dynamic comparators, and sample-and-hold circuits—to optimize for power, area, and signal integrity. Behavioral modeling of each functional block is accomplished through Verilog-A, enabling rapid prototyping and architecture validation prior to transistor-level implementation. This approach overcomes common challenges in direct schematic-level design by facilitating early design space exploration and functional verification. The proposed ADC architecture aims to achieve high performance and energy efficiency suitable for demanding GPR sensor applications

Ground Penetrating Radar, SAR, C-DAC, Resolution

"Design of SAR ADC for Ground Penetrating Radar Applications", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.12, Issue 10, page no.a714-a725, October-2025, Available :http://www.jetir.org/papers/JETIR2510089.pdf

"Design of SAR ADC for Ground Penetrating Radar Applications", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.12, Issue 10, page no. ppa714-a725, October-2025, Available at : http://www.jetir.org/papers/JETIR2510089.pdf