• KELLA SUDHA
• N.CHANDRASEKHAR

A Binary Full Adder is a critical component in microprocessor and digital signal processor data pipelines since it is used in almost all arithmetic operations. It serves as the foundation for critical activities like as multiplication, division, and addresses computation for cache or memory accesses, and is typically integrated into arithmetic logic units and floating-point units. As a result, improving their speed has significant implications for high-performance applications. This paper emphasizes the fundamental function of addition in digital computer systems and presents three new gate-level complete adder architectures. These designs are created using components from a typical cell library: the first uses XNOR and multiplexer gates (XNM), the second combines XNOR, AND, Inverter, multiplexer, and complex gates (XNAIMC), and the third uses XOR, AND, and complex gates. These designs are compared to several existing gate-level complete adder implementations. The XNM-based full adder was recognized as area-efficient, whilst the XNAIMC-based full adder demonstrated a moderate mix of speed and area efficiency when compared to the other two designs. The circuit was successfully developed and constructed utilizing the Tanner EDA tool and 45nm technology.

Combinational Logic, Full Adders, XNOR, X0R, XNAIMC, Tanner EDA tool 45nm Technology

"AREA EFFICIENT AND HIGH SPEED FULL ADDER ARCHITECTURE USING X-NOR AND XOR BASED LOGIC IN 45NM CMOS TECHNOLOGY ", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.12, Issue 12, page no.d194-d200, December-2025, Available :http://www.jetir.org/papers/JETIR2512325.pdf

"AREA EFFICIENT AND HIGH SPEED FULL ADDER ARCHITECTURE USING X-NOR AND XOR BASED LOGIC IN 45NM CMOS TECHNOLOGY ", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.12, Issue 12, page no. ppd194-d200, December-2025, Available at : http://www.jetir.org/papers/JETIR2512325.pdf