• Chittidi Haritha Sai Lakshmi Annapurna
• Avala Mallikarjuna Prasad

As CMOS technology moves deeper into the sub-micron regime, SRAM the memory type that dominates on-chip storage in most System-on-Chip designs spends an increasing share of its power budget on standby leakage rather than active switching. This work takes an existing aspect-ratio-optimized 6T SRAM bit-cell, previously designed in 45 nm CMOS (GPDK045) at 1.2 V for a favourable combination of speed and leakage, and augments it with a single footer NMOS transistor placed between the cell’s ground terminal and the true ground rail so the array can be power-gated during idle periods. Sized at a 600 nm width and a 45 nm channel length, this sleep device is turned fully ON whenever the cell is read or written and turned OFF once it returns to standby, breaking the sub-threshold leakage path while leaving the stored data node undisturbed. The complete cell, with and without the sleep transistor, was built and simulated in Cadence Virtuoso (GPDK045 nm) and characterized using both transient testing and 1000-run Monte Carlo analysis. Standby leakage power drops from 108.685 pW for the un-gated baseline to 20.9247 pW with the footer transistor in place, an approximately 80.7 % reduction, and this saving comes at almost no cost to active-mode behaviour: Write-1 delay actually improves, from 41.7843 ps to 36.4542 ps (12.8 % faster), write power falls from 6.9424 µW to 4.7611 µW (31.4 % lower), and Read-0/Read-1 delay together with read power shift by under 3.4 %. Taken together, these numbers indicate that a single, correctly sized footer sleep transistor is an inexpensive and effective way to cut SRAM standby leakage without sacrificing the speed or stability gained from aspect-ratio sizing.

"Design And Performance Analysis Of An Optimized Aspect-Ratio 6T Sram With Sleep-Transistor Based Power Gating For Standby Leakage Power Reduction", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.13, Issue 9, page no.c322-c328, September-2026, Available :http://www.jetir.org/papers/JETIR2609235.pdf

"Design And Performance Analysis Of An Optimized Aspect-Ratio 6T Sram With Sleep-Transistor Based Power Gating For Standby Leakage Power Reduction", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.13, Issue 9, page no. ppc322-c328, September-2026, Available at : http://www.jetir.org/papers/JETIR2609235.pdf