• K.V.Varaprasad
• K.Lakshmi Bhanu Prakash Reddy
• M.Vamsi Krishna Reddy
• S.Rishil Reddy

Modern VLSI techniques focus heavily on propagation of high speed and low power consumption. In this research paper, we present a hybrid 1-bit full adder using pass transistor logic design which employs both static CMOS logic and Pass Transistor Logic (PTL). We have compared our work against other state of art designs, for power consumption, speed and area constraints. We designed all the full-adders in cadence CMOS technology. At 1.8V power supply, the average power consumed by our design is 2.33µW, at 100MHz and the propagation delay 0.19 ns. It reduces transistor count and due to this power consumption reduces and hence Power delay product reduces.

Pass transistor logic, High speed, Low power, Power delay product

"Design and performance evaluation of low power & high speed hybrid 1-bit full adder for extensive PDP reduction using PTL", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.6, Issue 3, page no.25-30, March-2019, Available :http://www.jetir.org/papers/JETIRAK06005.pdf

"Design and performance evaluation of low power & high speed hybrid 1-bit full adder for extensive PDP reduction using PTL", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.6, Issue 3, page no. pp25-30, March-2019, Available at : http://www.jetir.org/papers/JETIRAK06005.pdf