• M Reddi Sekhar
• P Uma
• D Venkataramana
• B Pushpalatha
• D Viswanada reddy

Now a days the technology is improved in day to day life. The area, power and timing these three characteristics are very important in the design of low power VLSI systems. The CMOS technology is one of the fastest growing technologies where the analog and digital ICs are fabricated .Reduction of power consumption & reduction of area are the most important issues in CMOS circuit design. To optimize these parameters the proposed research work incorporated the 45nm FinFET technology for designing of 16: 4 encoder and 4:16 decoder by using universal gates. The 16:4 encoders occupied an area of 170.04um2, 4:16 decoder area is 189.88um2, power consumption of encoder and decoder are 1.173uW and 2.05uW .All simulation results and analysis are performed on 45nm using cadence virtuso tool. In this paper analyzes and optimizes area, power and size of the encoder and decoder using 45nm technologies.

FinFET, Digital and analog circuits, Encoder, Decoder

"AN EFFICIENT PRIORITY ENCODER & DECODER USING 45nm FinFET TECHNOLOGY", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.6, Issue 3, page no.143-149, March-2019, Available :http://www.jetir.org/papers/JETIRAK06027.pdf

"AN EFFICIENT PRIORITY ENCODER & DECODER USING 45nm FinFET TECHNOLOGY", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.6, Issue 3, page no. pp143-149, March-2019, Available at : http://www.jetir.org/papers/JETIRAK06027.pdf