• S.Rajeshwari
• J.Divya
• R.Karthika
• P.Tamilselvan

This paper presents a hardware architecture for face detection based system on using Haar features and curvelet transform. We describe the hardware design techniques including image scaling, integral image generation, pipelined processing as well as classifier, and parallel processing multiple classifiers to accelerate the processing speed of the face detection system. Also, we discuss the optimization of the proposed architecture which can be scalable for configurable devices with variable resources. The proposed architecture for face detection has been designed using Verilog HDL.Matlab and simulated using Modelsim software

AdaBoost, architecture, face detection, FPGA, Haar classifier,image processing, real-time.

"Face Recognition System using Curvelet Transform and Haar classifier", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.6, Issue 3, page no.331-335, March-2019, Available :http://www.jetir.org/papers/JETIRAK06066.pdf

"Face Recognition System using Curvelet Transform and Haar classifier", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.6, Issue 3, page no. pp331-335, March-2019, Available at : http://www.jetir.org/papers/JETIRAK06066.pdf