• N.Umapathi
• A. Malathi
• V. Sangeetha
• R.Vaishmitha
• K. Sai

: As we know the analysis of conventional carry select adder from its structure it is clear that there is a scope to reduce the area so it leads the low power consumption and high speed of operation, so it increases the DSP system performance and reduces the complexity of the processor. In this project we implemented the low power area efficient carry select adder by using binary to excess -1 converter. the main function of the binary to excess -1 converter is the logic comes from the lesser number of logic gates as compared to the n-bit ripple carry adder (RCA).CSLA designing with ripple carry adder is not efficient because it uses the multiple number of ripple carry select adders to generate the partial sum and carry by using the carry input. Then the final sum and carry is selected by the multiplexers . so this idea we are uses the binary to excess-1 converter it has less logic gates less power less cost, convenient to handle most used in VLSI systems

CSLA, RCA, BEC,

"DESIGN OF LOW POWER AREA EFFIECIENCY CSLA USING BEC-1 CONVERTER", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.6, Issue 4, page no.543-546, April-2019, Available :http://www.jetir.org/papers/JETIRAU06080.pdf

"DESIGN OF LOW POWER AREA EFFIECIENCY CSLA USING BEC-1 CONVERTER", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.6, Issue 4, page no. pp543-546, April-2019, Available at : http://www.jetir.org/papers/JETIRAU06080.pdf