UGC Approved Journal no 63975(19)

ISSN: 2349-5162 | ESTD Year : 2014
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Published in:

Volume 6 Issue 4
April-2019
eISSN: 2349-5162

UGC and ISSN approved 7.95 impact factor UGC Approved Journal no 63975

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Published Paper ID:
JETIRBC06039


Registration ID:
207147

Page Number

242-250

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Title

RESOURCE AND POWER ANALYSIS OF CSD-VHCSE BASED RECONFIGURABLE FIR FILTER ON VARIOUS FPGA’S

Abstract

Field programmable Gate Arrays (FPGAs) play important role in most of the reconfigurable electronic system design.FIR filters are the most important processing elements in almost all Digital Signal Processing elements(DSP) such as video and audio processing, Image processing. Software Defined Radio (SDR) and high rated communication systems need Reconfigurable Finite Impulse Response (RFIR) filters. In the Reconfigurable Finite Impulse Response (RFIR) channels, The channel coefficients can be powerfully changed amid the run time persistently. In Reconfigurable Finite Impulse Response (RFIR) channels the Reconfigurable Multiple Constant Multiplication (RMCM) elements are the resource and power consuming data path elements. Canonical Signed Digit-Vertical Horizontal Common Sub-expression (CSD-VHCSE) algorithm is used to reduce the resource and power consumption of Reconfigurable Finite Impulse Response filter. To implement this algorithm, full adder cells and adder depths of Finite Impulse Response filters are reducing binary coefficient to Canonical Signed Digit and by applying 4-bit Common Sub-expression vertically and 4-bit.8-bit Common Sub-expression horizontally in the filter design. The power utilization was diminished by diminishing the exchanging action of snake square of Reconfigurable Multiple Constant Multiplier. The CSD-VHCSE algorithm based reconfigurable FIR filter is designed and implemented in FPGA’s like Spartan-6, Spartan-6 Low Power, Virtex-5 and Virtex-6 Low Power, the resource and power utilizations are analysed

Key Words

RMCM-Reconfigurable Multiple Constant Multiplier, CSD-VHCSE – Canonical Signed Digit Representation based Vertical Horizontal Common Sub Expression Elimination, RFIR- Reconfigurable Finite Impulse Response Filter.

Cite This Article

"RESOURCE AND POWER ANALYSIS OF CSD-VHCSE BASED RECONFIGURABLE FIR FILTER ON VARIOUS FPGA’S", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.6, Issue 4, page no.242-250, April-2019, Available :http://www.jetir.org/papers/JETIRBC06039.pdf

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2349-5162 | Impact Factor 7.95 Calculate by Google Scholar

An International Scholarly Open Access Journal, Peer-Reviewed, Refereed Journal Impact Factor 7.95 Calculate by Google Scholar and Semantic Scholar | AI-Powered Research Tool, Multidisciplinary, Monthly, Multilanguage Journal Indexing in All Major Database & Metadata, Citation Generator

Cite This Article

"RESOURCE AND POWER ANALYSIS OF CSD-VHCSE BASED RECONFIGURABLE FIR FILTER ON VARIOUS FPGA’S", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.6, Issue 4, page no. pp242-250, April-2019, Available at : http://www.jetir.org/papers/JETIRBC06039.pdf

Publication Details

Published Paper ID: JETIRBC06039
Registration ID: 207147
Published In: Volume 6 | Issue 4 | Year April-2019
DOI (Digital Object Identifier):
Page No: 242-250
Country: --, -, - .
Area: Engineering
ISSN Number: 2349-5162
Publisher: IJ Publication


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