• R ABHIRAMI
• RITU RATRA

With constantly transforming specifications due to advancements in design flows and faster time to market, it is becoming challenging for the Very Large Scale Integration (VLSI) designers to accommodate different components in to the System On Chip (SoC). As the complexity depends on number of components being added into the design, the integration becomes singularly challenging. Computer Aided Design helps in capturing the intricacies and extensive details in an organized format which could be reused by the SoC integrator for efficient and expeditious progress. IP CAD views play a critical role in the System On Chip integration process as multi-purpose and multi voltage devices are coming into consideration together on a same yet minute platform. There is a need for innovative techniques targeted to achieve Simplified and Standardized generation process of CAD Views capable of handling huge IP portfolio and addressing needs of a big spectrum of EDA design flows. Rapidly changing technology along with an extensive multidisciplinary team and huge amount of data generated requires organization of essential data in an easily usable format for the various users at every stage in the Register Transfer Level (RTL) to Graphic Data System (GDSII) Flow. Intellectual Property (IP) Libraries which are generated contain the various circuit description models like electrical and physical models which are used for VLSI SoC Integration. This research paper deals with the various challenges which are faced in the IP and libraries CAD views generation. CAD views are generated by using various Electronic Design Automation (EDA) from companies like Cadence®, Synopsys® and Mentor Graphics®. The contribution of work towards addressing the challenges are in the form of suggesting simplification of process steps, methodologies which can shorten the execution cycle of the process and also which support the maximum reutilization of IP data. Various case studies from real projects are used as a basis for development of methodology. The proposed methodology has been successfully deployed in various automotive projects, Microcontrollers, Imaging Technologies and IoT based applications. The benefits from using this approach help in reduction of product development cycle time and early stages enablement of the SoC

CAD Views Generation, Productivity, SoC, Time to Market, VLSI

"Challenges And Solutions For Ip Cad View Generation For Efficient System On Chip Integration", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.6, Issue 4, page no.148-152, April-2019, Available :http://www.jetir.org/papers/JETIRBF06030.pdf

"Challenges And Solutions For Ip Cad View Generation For Efficient System On Chip Integration", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.6, Issue 4, page no. pp148-152, April-2019, Available at : http://www.jetir.org/papers/JETIRBF06030.pdf