• Mrs.A Anitha
• Ms. Amrutha H
• Ms.Pallavi S
• Ms.Vanaja devi vs
• Ms.Soubhagya

The main focus of this paper is to design a “LOW POWER FLASH ADC” For ultra-wide and applications using CMOS 90-Nm Flash ADC consists of a reference generator, array of comparators, 1-out-of N code generator, fat tree encoder and output D-latches. The demanding issues in the design of a low power flash ADC is the design of low power latched comparator. The proposed comparator in this paper is designed using 90-nm technology at 0.8V DC voltage source using Cadence tool. The simulation results of a 8-bit ADC is shown for a sampling frequency up to 1.2GHz showing an average power dissipation of 7.67mW.

Flash ADC, preamplifier based latch comparator, low power consumption.

"A LOW POWER COMPARATOR DESIGN FOR 8-BIT FLASH ADC IN 90-nm CMOS", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.6, Issue 5, page no.599-601, May-2019, Available :http://www.jetir.org/papers/JETIRCJ06124.pdf

"A LOW POWER COMPARATOR DESIGN FOR 8-BIT FLASH ADC IN 90-nm CMOS", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.6, Issue 5, page no. pp599-601, May-2019, Available at : http://www.jetir.org/papers/JETIRCJ06124.pdf