• Sheetal Nagar
• Govind Singh Patel
• Seema Nayak

In the new era of smart digital gadgets, the low power of the devices is on the highest priority. All the electronic gadgets contain the microprocessor and microcontroller which contains the arithmetic & logic unit and accumulator. All arithmetic operators like addition subtraction multiplication and division contain the highest accuracy in result to achieve the output different tasks. The architecture of microprocessors or the arithmetic units must be low power consumption and must be efficient. There are many multipliers in the literature. Every multiplier has its merits and demerits. As per the application multiplies can be select. The most important multiplier techniques are Vedic multiplier Russian peasant Wallace modified & logarithm will focus on the latest design of multiplier in this paper.

Low Power Design, Wallace, Dadda, Speed, area.

"Design Of Low Power Digital Multiplier", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.6, Issue 1, page no.1392-1399, January 2019, Available :http://www.jetir.org/papers/JETIRDW06223.pdf

"Design Of Low Power Digital Multiplier", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.6, Issue 1, page no. pp1392-1399, January 2019, Available at : http://www.jetir.org/papers/JETIRDW06223.pdf